Method and apparatus for hardware-configurable multi-policy coherence protocol
US8135916B1 · kind B1 · utility
11Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2009 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Apr 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.