ECC implementation in non-ECC components
US8135935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.