Method and structure for gate height scaling with high-k/metal gate technology
US8138037B2 · kind B2 · utility
40Cited by
2References
16Claims
0Family size
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Key dates
| Filing date | Mar 2, 2010 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Aug 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.