Michael P. Chudzik
131Patents
16h-index
182Co-inventors
89Inventor score
Filing activity: Jul 20, 2000 → Jan 9, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7030481B2 | High density chip carrier with integrated passive devices | Electricity | 320 | Expired |
| US6962872B2 | High density chip carrier with integrated passive devices | Electricity | 298 | Expired |
| US7622341B2 | Sige channel epitaxial development for high-k PFET manufacturability | Electricity | 120 | Active |
| US6930060B2 | Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric | Electricity | 76 | Expired |
| US8138037B2 | Method and structure for gate height scaling with high-k/metal gate technology | Electricity | 40 | Active |
| US7091118B1 | Replacement metal gate transistor with metal-rich silicon layer and method for making the same | Electricity | 36 | Expired |
| US6451662B1 | Method of forming low-leakage on-chip capacitor | Electricity | 35 | Expired |
| US7741188B2 | Deep trench (DT) metal-insulator-metal (MIM) capacitor | Emerging Cross-Sectional Technologies | 28 | Active |
| US6361598B1 | Method for preparing high temperature superconductor | Chemistry; Metallurgy | 23 | Expired |
| US7838908B2 | Semiconductor device having dual metal gates and method of manufacture | Electricity | 23 | Active |
| US8373239B2 | Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric | Electricity | 23 | Active |
| US6555430B1 | Process flow for capacitance enhancement in a DRAM trench | Emerging Cross-Sectional Technologies | 21 | Expired |
| US8354309B2 | Method of providing threshold voltage adjustment through gate dielectric stack modification | Electricity | 20 | Active |
| US7863126B2 | Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region | Electricity | 20 | Active |
| US7504700B2 | Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method | Electricity | 18 | Expired |
| US8232148B2 | Structure and method to make replacement metal gate and contact metal | Electricity | 16 | Active |
| US9679810B1 | Integrated circuit having improved electromigration performance and method of forming same | Electricity | 16 | Active |
| US7732872B2 | Integration scheme for multiple metal gate work function structures | Electricity | 16 | Active |
| US7750418B2 | Introduction of metal impurity to change workfunction of conductive electrodes | Electricity | 16 | Active |
| US6905944B2 | Sacrificial collar method for improved deep trench processing | Electricity | 16 | Expired |
| US7754594B1 | Method for tuning the threshold voltage of a metal gate and high-k device | Electricity | 16 | Active |
| US8420473B2 | Replacement gate devices with barrier metal for simultaneous processing | Electricity | 16 | Active |
| US9437496B1 | Merged source drain epitaxy | Electricity | 15 | Active |
| US7446380B2 | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS | Electricity | 14 | Expired |
| US6664161B2 | Method and structure for salicide trench capacitor plate electrode | Electricity | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.