Process for fabricating a nanowire-based vertical transistor structure
US8138046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jun 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13′) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.