CMOS image sensor having a crosstalk prevention structure
US8138530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/802
Abstract
In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.