Castellated gate MOSFET tetrode capable of fully-depleted operation

US8138544B2 · kind B2 · utility

Inventor

• John J. Seliskar · Charlottesville, US

Key dates

• Filing date: Feb 23, 2010
• Grant date: Mar 20, 2012
• Expiry date: Jul 10, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions. First and second gate structures are provided in the form of pluralities of spaced, castellated first and second gate elements interposed between the primary and secondary channel elements, respectively, with first and second top gate members interconnecting the first and second gate elements at their upper vertical ends to cover the primary …