Systematic error correction for multi-level flash memory
US8139412B2 · kind B2 · utility
5Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Mar 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.