Three dimensional chip fabrication
US8140297B2 · kind B2 · utility
11Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Feb 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip. The components from the 2D chip are layered and coupled to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.