Optimal bus operation performance in a logic simulation environment
US8140314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2008 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jan 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.