Method and arrangement providing for implementation granularity using implementation sets
US8141010B1 · kind B1 · utility
2Cited by
29References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2008 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.