Patent · US Active

Semiconductor manufacturing process

US8142086B2 · kind B2 · utility

0Cited by

5References

9Claims

0Family size

Assignee

NANYA TECHNOLOGY CORPORATION · TW

Inventors

Pei-Lin Huang · Daxi District, TW
Yi Wang · Ann Arbor, US
Chun-Yen Huang · Taoyuan, TW

Key dates

Filing date	Oct 19, 2010
Grant date	Mar 27, 2012
Priority date	—
Expiry date	Oct 19, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG03D5/00
WIPO fieldOptics
WIPO sectorInstruments

Abstract

A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.