Silicon wafer and method for manufacturing the same
US8142885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2007 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24992
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Silicon wafers and a process for their manufacture wherein both slip dislocation and occurrence of warpage are suppressed include heat treatment to provide wafers having plate-shaped BMDs, a density of BMDs whose diagonal lengths are in a range of 10 nm to 120 nm, of BMDs present in the bulk of the wafer at a distance of 50 μm or more is 1×1011/cm3 or more, and the density of BMDs whose diagonal lengths are 750 nm or more in the wafer bulk is 1×107/cm3 or less, and the interstitial oxygen concentration is 5×1017 atoms/cm3 or less. The process involves low and high temperature heat treating at under defined temperature ramping rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.