Structure and method for forming a salicide on the gate electrode of a trench-gate FET
US8143125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.