Method for forming a vertical MOS transistor

US8143126B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Jingjing Chen · Fuzhou, CN
• Ganming Qin · Chandler, US
• Edouard D. de Frésart · Tempe, US
• Pon Sung Ku · Gilbert, US

Key dates

• Filing date: May 10, 2010
• Grant date: Mar 27, 2012
• Expiry date: Jul 27, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/518

Abstract

A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.