Fabrication of interconnects in a low-k interlayer dielectrics
US8143159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2010 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.