Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size
US8144509B2 · kind B2 · utility
56Cited by
2References
29Claims
0Family size
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Key dates
| Filing date | Jun 27, 2008 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Sep 21, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/933
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.