Method to improve the write speed for memory products
US8144526B2 · kind B2 · utility
2Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2010 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.