Semiconductor memory device and method for generating output enable signal
US8144530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jun 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0805
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.