Latency control circuit, semiconductor memory device including the same, and method for controlling latency
US8144531B2 · kind B2 · utility
6Cited by
7References
15Claims
0Family size
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Key dates
| Filing date | Dec 8, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.