Balanced sense amplifier for single ended bitline memory architecture
US8144537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.