Address translation with multiple translation look aside buffers
US8145876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2007 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When the data processing device is in a hypervisor mode, a second TLB is accessed in response to the request to access the page tables. If the virtual address is located in the second TLB, the hypervisor page tables are bypassed and the second TLB provides a physical address or information to access another table in the set of page tables. By bypassing the hypervisor page tables, the time to translate an address in the hypervisor mode is reduced, thereby improving the efficiency of the data processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.