Patent · US Active

Address generation for quadratic permutation polynomial interleaving

US8145877B2 · kind B2 · utility

2Cited by

1References

19Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Ben Jones · San Diego, US
Colin Stirling · Edinburgh, GB

Key dates

Filing date	Mar 31, 2008
Grant date	Mar 27, 2012
Priority date	—
Expiry date	Nov 20, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/2739
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.