Integrated circuit fabrication process convergence
US8146023B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for selecting a process for a new integrated circuit design. Structures that are used in existing integrated circuit designs are identified, as well as the photolithography processes that are used to fabricate integrated circuits that are based on the existing designs. A process window is determined for each structure/process combination by running tests on different combinations of process variables, and a database of the process windows is compiled. The structures that are to be used in the new integrated circuit design are identified, and the process windows associated with the identified structures for the new integrated circuit design are selected from the database. The selected process windows for the identified structures are overlaid, grouped by common process, thereby creating a resultant process window for each process. One of the processes is selected, based at least in part on comparative sizes of the resultant process windows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.