Data receiver of semiconductor integrated circuit
US8149953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Oct 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09425
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.