Patent · US Active

Method, system and apparatus for memory address mapping for sub-socket partitioning

US8151081B2 · kind B2 · utility

1Cited by

3References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ajay Harikumar · Bengaluru, IN
Tessil Thomas · Bengaluru, IN
Biju Puthur Simon · Bengaluru, IN

Key dates

Filing date	Nov 7, 2008
Grant date	Apr 3, 2012
Priority date	—
Expiry date	Oct 12, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0284
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.