Method for address translation in virtual machines
US8151085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2009 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.