Camouflaging a standard cell based integrated circuit
US8151235B2 · kind B2 · utility
16Cited by
31References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | May 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.