Mask and manufacturing method of a semiconductor device and a thin film transistor array panel using the mask
US8153339B2 · kind B2 · utility
6Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jun 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about −70° to about +70°.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.