Semiconductor surround gate SRAM storage device
US8154086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2010 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.