Semiconductor package and methods of manufacturing the semiconductor package
US8154122B2 · kind B2 · utility
0Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jan 31, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.