Method and apparatus for reducing power consumption in a content addressable memory
US8154900B2 · kind B2 · utility
0Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Sep 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.