Circuit providing load isolation and noise reduction
US8154901B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.