Full CMOS SRAM
US8154910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2010 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.