Single-ended bit line based storage system
US8154936B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Feb 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.