Embedded parity coding for data storage

US8156400B1 · kind B1 · utility

Assignee

• Marvell International Ltd. · BM

Inventors

• Engling Yeo · San Jose, US
• Eugene Pan · Milpitas, US
• Henri Sutioso · Saratoga, US
• Jun Xu · Longbeilingcun, CN
• Shaohua Yang · Santa Clara, US
• Panu Chaichanavong · Sunnyvale, US
• Gregory Burd · San Jose, US
• Zining Wu · Los Altos, US

Key dates

• Filing date: Jul 11, 2007
• Grant date: Apr 10, 2012
• Expiry date: Feb 7, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M13/1515
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A decoder memory system comprises a first memory comprising at least a portion of a parity check matrix H. A second memory receives the portion from the first memory and that is associated with a previous decoding iteration. A third memory communicates with the first memory, receives the parity check matrix H and is associated with a current decoding iteration. A fourth memory comprises likelihood ratios. A control module generates a LDPC decoded signal based on the parity check matrix H, the previous decoded iteration and the likelihood ratios.