Combination of a substrate and a wafer
US8156981B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Inventor
Key dates
| Filing date | Nov 1, 2010 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Nov 1, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention pertains to a combination of a substrate (6) and a wafer (15), wherein the substrate (6) and the wafer (15) are arranged parallel to one another and bonded together with the aid of an adhesive layer (8) situated between the substrate (6) and the wafer (15), and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer (8) is only applied annularly between the substrate (6) and the wafer (15) in the edge region of the wafer (15).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.