Method of forming stacked dies
US8158456B2 · kind B2 · utility
123Cited by
35References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Mar 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.