Graded junction high voltage semiconductor device
US8159001B2 · kind B2 · utility
27Cited by
30References
45Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2006 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jan 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate the p-well(s) and the n-well, breakdown voltage characteristic is improved without the cost of an additional mask or process change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.