Signaling with superimposed clock and data signals
US8159274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jan 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.