6T SRAM cell with single sided write
US8159863B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 19, 2010 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Jan 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.