Efficient implementation of arithmetical secure hash techniques
US8160242B2 · kind B2 · utility
6Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Nov 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.