Patent · US Active

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

US8161219B2 · kind B2 · utility

0Cited by

6References

28Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Bruennert · Munich, DE
Peter Gregorius · Munich, DE
Georg Braun · Hersbruck, DE
Andreas Gartner · Wien, AT
Hermann Ruckerbauer · Radolfzell, DE
George Alexander · Durham, US
Johannes Stecker · Birkenfeld, DE

Key dates

Filing date	Dec 4, 2008
Grant date	Apr 17, 2012
Priority date	—
Expiry date	Nov 14, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/409
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.