Wait loss synchronization
US8161247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Aug 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.