Memory interface with dynamic selection among mirrored storage locations
US8161252B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | May 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and methods provide data from multiple storage locations to a processor. A data block containing data required by a processor is stored in two or more locations, e.g., in a local memory and a system memory, both of which are accessible to the processor's memory interface. The memory interface directs each read request for mirrored data to one or another of the mirror locations. Selection of a mirror location to be read is based on substantially real-time information about which mirror location is best able to handle the request. For instance, the selection of a mirror location to access can be based at least in part on information about the level of activity on various buses that connect the processor to the mirror locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.