Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
US8161355B2 · kind B2 · utility
11Cited by
18References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2009 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Dec 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.