Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8161367B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.