Logic circuit and method of logic circuit design
US8161427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2010 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Aug 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.