Method and apparatus for processing assertions in assertion-based verification of a logic design
US8161439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2008 |
| Grant date | Apr 17, 2012 |
| Priority date | — |
| Expiry date | Oct 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.