Patent · US Active

Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

US8161447B2 · kind B2 · utility

1Cited by

20References

20Claims

0Family size

Assignee

LSI · US

Inventors

Juergen Dirks · Holzkirchen, DE
Matthias Dinter · Holzkirchen, DE
Ralf Leuchter · Munich, DE

Key dates

Filing date	May 11, 2009
Grant date	Apr 17, 2012
Priority date	—
Expiry date	Mar 6, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.